1. Field
The embodiments are generally directed to Network-on-Chip architecture designs. More particularly, the embodiments are directed to efficient communication between nodes in a Network-on-Chip architecture.
2. Background Art
As technology scales down, an increasing number of designs are getting integrated on the same silicon die, causing demand for on-chip communication architecture. Many system-on-a-chip (SoC) designs use commercially available bus-based topologies, such as VME, AMBA, and CoreConnect, for on-chip communication because of their simple architectures and low area costs. Bus-based topologies clearly cannot satisfy the very demanding needs of today's on-chip communication because of the lack of scalability; only one component pair can communicate at a time, and the load capacitance of the entire bus has to be driven during each data transfer.
Switch-based network design was proposed as an alternative to bus-based topologies. A switching network provides high-performance on-chip communication for SoC designs. There are different on-chip communication architectures based on the switch-based design.
There is a need for an easily sealable communication architecture between nodes that both provides high performance and reduces the node complexity.